Quad Data Rate (QDR™) SRAM devices, which are high performance SRAMs used for communication applications and the like include separate data input and data output buses, and include separate/concurrent read and write ports. With respect to the latest information on the QDR SRAM, the following Nonpatent Document 1 and the like are referred to. QDR is a trademark of CYPRESS, HitaCHIT, IDT, Micron, NEC, and Samsung.
While a DRAM (dynamic random access memory) device requires a periodic refresh operation and a pre-charge operation of a bit line, a SRAM device is excellent in terms of a data access cycle. On the other hand, in the SRAM device, each cell is composed by four transistors (two selection transistors connected to a pair of bit lines and two transistors with their gates and drains cross-connected to each other in the case of a high resistive load type cell) or six transistors (in the case of an active element load type). The memory cell in the DRAM device is composed by one transistor and one capacitor, for example. A DRAM is superior to an SRAM in terms of a chip area, power dissipation, and a cost. Thus, there is proposed the DRAM which aims at improvement in device integration, power dissipation, and the cost while providing advantages of a conventional ZBT (zero bus turnaround) SRAM device having similar pin outs, timing and function set to those of the SRAM (refer to the following Patent Document 1, for example). The Patent Document 1 described an object of providing the enhanced bus turnaround DRAM with pinouts, the timing, and function sets similar to those of the ZBT SRAM device and having same advantages as the ZBT SRAM device. The device, however, is not ZBT-SRAM compatible. More specifically, the memory device described in the above-mentioned Patent Document 1 includes a WAIT terminal for informing a controller provided outside the memory device that a memory array is in a state where it cannot be used for data access. In a refresh cycle, read/write operations must be interrupted. The Patent Document 1 discloses a configuration in which an SRAM memory (or an SRAM cache) is provided for a (DRAM) memory array as a row cache.
There are also known a method and a device in which a read and a write are performed in succession in a same cycle (refer to the following Patent Document 2, for example). These method and device utilizes an advantage that, by employing a data input bus and a data output bus in a separate I/O DDR (Double Data Rate) or QDR RAM, a data rate can be doubled or increased more in a same cycle time. When the device receives a read command in one cycle, a step of performing a read operation in synchronization with a clock signal and a step of performing a write operation in synchronization with a signal that operates during the read is executed in one cycle. There is further known a configuration that includes an SRAM array connected to a DRAM memory via a transfer circuit (refer to the following Patent Document 3, for example). As a general configuration of a known cache memory that will be described later, the following Non-Patent document 2 and the like are referred to.
[Nonpatent Document 1]
“QDR SRAM—The High Bandwidth SRAM Family” Internet (searched on May 2, 2003) <URL:http://www.qdrsram.com/>
[Nonpatent Document 2]
John. L. Hennesy and David A. Patterson. “Computer Organization and Design”, 7.2 Caches, p463, Morgan Kaufmann Publihshers Inc. 1994.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-283587A (p. 2, FIG. 1)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2002-313082A (p. 6, FIG. 3)
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-A-11-86532 (p. 4, FIG. 1)